1. Field of the Invention
The present invention generally relates to computer systems, and more particularly to an improved method of steering program instructions to a specific execution unit in a processor, and to an improved processor design.
2. Description of the Related Art
High-performance computer systems use multiple processors to carry out the various program instructions embodied in computer programs such as software applications and operating systems. These processors typically have a processor core comprising a single integrated circuit superscalar microprocessor having various execution units (fixed-point units, floating-point units, and load/store units), registers, buffers, memories, and other functional units, which are all formed by integrated circuitry. The processor cores may operate according to reduced instruction set computing (RISC) techniques, and may employ both pipelining and out-of-order execution of instructions to further improve the performance of the superscalar architecture.
Simultaneous multithreading (SMT) is a processor design that combines hardware multithreading with superscalar processor technology to allow multiple threads to issue instructions each cycle. Unlike other hardware multithreaded architectures in which only a single hardware context (i.e., thread) is active on any given cycle, SMT permits all thread contexts to simultaneously compete for and share processor resources. To reduce issue latency between a dependent instruction and the independent instruction on which it depends (i.e., the instruction that is producing its data), it is desirable to be able to steer the dependent instruction to the same execution unit where the independent instruction is being executed. On a microprocessor with multiple execution units, it can be quite difficult to steer the dependent instruction to the same execution unit on which the independent instruction is being executed. This is because, with so many operations being performed in a short period of time, all of which may be competing for use of the same execution units, resource conflicts invariably occur.
To reduce the competition for the shared execution units and other shared resources between the threads, “steering” techniques have been developed to steer the various instructions in the threads to particular resources based on thread priority (e.g., a thread with a higher priority might be given preferential access to shared resources over a lower priority thread). In the prior art, these steering techniques were used as part of a queuing process prior to issue time, that is, the instructions were statically assigned an execution unit. Each execution unit was fed by its own issue queue, and once an instruction was placed into the issue queue of a particular execution unit, it would have to issue to that particular execution unit.
While these steering techniques of the prior art function adequately, they do not allow dynamic modification of the instruction destination, once the instruction is queued up for issuance. This can lead to problems because there my be certain downstream events occurring, i.e., problems with execution units, changed priorities, and the like, that affect the operation of the execution units and which, if known prior to issue time, might have changed the way in which the instructions were steered. Accordingly, it would be desirable to devise a method whereby instructions could be dynamically steered upon issuance.